Scribe based bond pads for integrated circuits

ABSTRACT

An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/607,564, filed on Dec. 1, 2006, which is incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices andspecifically to a method of separating product and test die from asemiconductor wafer.

BACKGROUND OF THE INVENTION

Many microcontrollers and microprocessors contain embedded memories suchas ROM. Typically, it is not possible to modify the memory of embeddedROM after manufacture. In the case of Write Once Memory, it is onlypossible to modify the memory once.

It is standard in the industry to develop software applications forembedded processors. In order to develop and test software on real-time(or full speed) silicon it is necessary to bond out the read only memoryon externally accessible bond out pads. The internal memory is isolatedand replaced by external memory connected to the bond out pads.

Currently, manufacturers use bond out memory in development silicon.However, the standard approach requires that the provision of bond outpads occupy a significant amount of silicon area, resulting in asignificant increase in product cost. Manufacturers have addressed thisissue by either absorbing the costs or by manufacturing two variants ofsilicon, one for development purposes that includes bond out pads and aproduction version that does not include bond out pads. Both approacheslead to an increase cost of production.

Accordingly, what is desired is a cost-efficient method of manufacturingsemiconductor wafers that can be used for both product and developmentpurposes. The present invention addresses this need.

BRIEF SUMMARY OF THE INVENTION

A method and system for utilizing a semiconductor wafer is disclosed.The wafer comprises a plurality of semiconductor die and a plurality ofscribe areas interspersed between. The method and system comprisesforming bond out pads in the scribe areas such that the bond out padsare disposed on the semiconductor wafer between the plurality ofsemiconductor die. Additionally, the method and system comprisesseparating the semiconductor wafer into individual die such that whenthe semiconductor wafer is separated in a first manner at least oneproduct die is provided. Furthermore, when the semiconductor wafer isseparated in a second manner at least one test die is provided.

An apparatus including a semiconductor substrate is disclosed. A firstsemiconductor die is disposed on the semiconductor substrate. A firstbond out pad is disposed on the semiconductor substrate adjacent to thefirst semiconductor die. A first sawn semiconductor die is disposed onthe semiconductor substrate adjacent to the first semiconductor die andthe first bond out pad.

Accordingly, it is an advantage of the present invention to provideseparation methods that provide either a plurality of product die or aplurality of test die from a semiconductor wafer.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

FIG. 1 shows a top version of a semiconductor wafer which features aplurality of semiconductor die, represented by small squares.

FIG. 2 shows a magnified area of a 3×3 semiconductor die cluster andbond out pad circuitry in a scribe area on a semiconductor wafer.

FIG. 3 shows a magnified area of a 3×3 semiconductor die cluster, sawlines on semiconductor dice adjacent to a test/emulation die, andcorresponding bond out pads.

FIG. 4 shows a sawn semiconductor wafer structure featuring anemulation/test die with corresponding bond out pads, test circuitry, andadjacent, sawn-semiconductor dice.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates generally to semiconductor devices andspecifically to a method of separating product and test die from asemiconductor wafer. The following description is presented to enableone of ordinary skill in the art to make and use the invention and isprovided in the context of a patent application and the genericprinciples and features described herein will be readily apparent tothose skilled in the art. Thus, the present invention is not intended tobe limited to the embodiments shown, but is to be accorded the widestscope consistent with the principles and features described herein.

FIG. 1 shows a top view of a semiconductor wafer 100 that features aplurality of semiconductor die 101, denoted by small squares.Semiconductor 100 also features bond out pads and test circuitry (shownin subsequent figures). A semiconductor wafer 100 may be designated as aproduct or test/development wafer. In the event semiconductor wafer 100is designated for product, the semiconductor die is subsequentlyseparated into individual semiconductor die, which includesdestructively removing the test circuitry and bond out pads disposed inthe scribe area. Alternatively, in the event that a semiconductor waferis designated for testing, test dice are separated by sawing throughadjacent semiconductor dice while maintaining the integrity of the testcircuitry and bond out pads.

According to an embodiment, the term “separating” (and other verb tensesof the term) refers to a process of partitioning a semiconductor waferinto individual, semiconductor die or dice. The term may also bereferred to as singulating, dividing, or severing.

For an embodiment, each semiconductor die 101 disposed on semiconductorwafer 100 are identical and each contain memory circuitry for storingdata securely. For the embodiment, semiconductor die 101 is amicrocontroller and the memory circuit is provided in the form ofread-only memory (ROM). For alternative embodiments, semiconductor die101 is a microprocessor.

For an embodiment, semiconductor wafer 100 is processed usingconventional semiconductor fabrication techniques to form semiconductordie 101 thereon. During the fabrication of semiconductor die 101, testcircuitry and bond out pads are also formed, according to an embodiment.

As stated previously, a semiconductor wafer may be designated as aproduct or test/development wafer. In the event a semiconductor wafer isdesignated for product, the semiconductor die is subsequently separatedinto individual semiconductor die, which includes destructively removingthe test circuitry and bond out pads disposed in the scribe areas.

FIG. 2 shows an example layout of a 3.times.3 semiconductor die cluster210 when a semiconductor wafer is designated for product. Those havingordinary skill in the art will appreciate that this layout is notlimited to a 3.times.3 semiconductor die cluster and that asemiconductor die cluster may incorporate more or less semiconductordice thereon. For the embodiment when a semiconductor wafer isdesignated for product, the semiconductor wafer is separated intoindividual semiconductor dice 201. Separating a semiconductor wafer intoindividual semiconductor dice 201 may be achieved by use of a sawingtechnique, laser obliteration, diamond scribe or additional waferprocessing techniques such as selective chemical etching. For anembodiment, a sawing technique is used to separate a semiconductor waferinto individual semiconductor dice for product.

For the embodiment when a sawing technique is used, a first sawingprocedure is made along a set of scribe lines 203 in scribe area 209.For embodiments, scribe area 209 has a width of approximately 70microns. In other words, the space between adjacent semiconductor diedisposed on a semiconductor wafer is at least approximately 70 microns.In the first sawing procedure, a saw blade having a width less than thewidth of scribe area 209 is used to cut a shallow depth sufficient tocut into the surface of a semiconductor wafer, but not so deep as to cutcompletely through the semiconductor wafer. For the embodiment, thissawing procedure destructively removes the test circuitry and bond outpads 202 in scribe area 209.

Next, according to an embodiment, a semiconductor wafer is subjected toa second sawing procedure such that a second cut is made along the pathmade by the first saw cut within scribe area 209. For an embodiment, asaw blade having a narrow width is used to cut completely through thesemiconductor wafer. The second sawing procedure thus completely seversand separates the wafer into individual semiconductor dice, whichprovides enhancing security against unauthorized access.

It will be appreciated that since the test circuitry and bond out pads202 have been removed from their respective device dies, at this pointno further testing of the device is ordinarily possible. It will befurther appreciated that since the test circuitry and bond out pads 202are destroyed in their removal, their visual inspection or reverseengineering is made practically impossible, further enhancing securityof the devices against access by a hacker. It will also be appreciatedthat any remaining fragments of test circuitry and bond out pads cannotnow be used to probe electrical activity or features of the devicessince these fragments of inoperable test circuitry and bond out pads arerendered and remain isolated in the absence of the enabling signals fromthe test circuitry which was present but which has now been destroyed.

It will be appreciated that although in the above described embodimentfeatures in the form of test circuitry and bond out pads aredestructively removed to enhance the security of the finished device,the security of the finished device could be alternatively oradditionally enhanced by the destructive removal of other features suchas expanded test mode circuitry or circuitry for unscrambling (otherwisescrambled) access to the devices' bus, central processing unit ormemory.

For an embodiment, a semiconductor wafer may be designated for testingor emulation. FIG. 3 shows a magnified area of a 3×3 semiconductor diecluster 310, saw lines 305 projected on semiconductor dice 301 adjacentto a test/emulation die 304, and corresponding bond out pads 302. For anembodiment, a semiconductor wafer designated for test or emulationundergoes a separation process relative to the separation process usedto separate die disposed on product wafers, as described above.

For an embodiment when a semiconductor wafer is designated a test oremulation wafer, a subsequent separation procedure is in accordance withthe following: a first sawing procedure along saw lines 305 projected onsemiconductor dice 301 to a pre-determined depth such that grooves arecut in adjacent semiconductor dice 301; a second sawing procedure alongthe grooves formed by the first sawing procedure such that the adjacentsemiconductor dice 301 are severed in halves, fourths, or any fractionof the original size of semiconductor dice 301.

FIG. 4 shows a sawn-semiconductor wafer structure 411 featuring anemulation/test die 404 with corresponding bond out pads 402, testcircuitry 413, and adjacent, sawn-semiconductor dice 412. As shown,emulation/test die 404 is separated from its parent semiconductor wafer,while the structural integrity of bond out pads 402 and test circuitry413 remain intact. Additionally, FIG. 4 shows a jagged edge 414, whichsignifies the aforementioned sawing procedure. For an embodiment, a“jagged edge” is defined as any uneven surface. For example, adjacent,sawn-semiconductor dice 412 may have jagged edges due to the saw-cuttingmethod described above.

It will be further appreciated that the bond out pads may bemanufactured such that electrostatic damage (ESD) is minimized. ESD istypically caused by charge build-up in interconnects withinsemiconductor devices. Often, charges are introduced withinsemiconductor devices during fabrication processes, such as, but notlimited to chemical mechanical polishing, interlayer dielectric etch,and plasma deposition or etch. For an embodiment, ESD protection may beachieved by forming a salicide layer on drain regions and embeddingantenna diodes within the bond out pad device.

Typically, devices are conventionally manufactured with ESD protectionfor human handling (approximately 6 kV), or machine model (approximately200V). This is necessary for protection/yield reason. For the scribebond pad application, there is limited available space in the scribearea for placement of bond pads, buffer circuit, and ESD protectioncircuitry. For semiconductor wafers that have been designated foremulation, the size of ESD protection circuitry can be reduced to allowmore space for bond pads and complementary circuitry (buffer and ESDprotection circuitry) within the scribe area. For an embodiment, the ESDprotection circuitry may be lowered below a level that is acceptable forproduction devices. However, for embodiments, a reduction in ESDprotection is a less critical for emulation (test die) as the volumes ofdie for testing is small relative to the large volume of production die.

For various embodiments, ESD protection circuitry may be disposedadjacent to or under the bond out pads such that ESD protection isprovided.

Although the present invention has been described in accordance with theembodiments shown, one of ordinary skill in the art will readilyrecognize that there could be variations to the embodiments and thosevariations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe appended claims.

1. An apparatus comprising: a semiconductor substrate; a firstsemiconductor die disposed on the semiconductor substrate; a first bondout pad disposed on the semiconductor substrate adjacent to the firstsemiconductor die; and a first sawn semiconductor die disposed on thesemiconductor substrate adjacent to the first semiconductor die and thefirst bond out pad.
 2. The apparatus of claim 1, wherein the firstsemiconductor die includes a test die.
 3. The apparatus of claim 1,wherein the first semiconductor die includes an emulation die.
 4. Theapparatus of claim 1, wherein the bond out pad is disposed between thefirst semiconductor die and the first sawn semiconductor die.
 5. Theapparatus of claim 1, wherein the first bond out pad is disposed along afirst scribe line of the semiconductor substrate and completely within ascribe area of the semiconductor substrate.
 6. The apparatus of claim 1,comprising a second sawn semiconductor die disposed on the semiconductorsubstrate adjacent to the first semiconductor die.
 7. The apparatus ofclaim 6, comprising a second bond out pad disposed on the semiconductorsubstrate between the first semiconductor die and the second sawnsemiconductor die.
 8. The apparatus of claim 6, wherein the second bondout pad is disposed along a second scribe line of the semiconductorsubstrate and completely within a scribe area of the semiconductorsubstrate.
 9. The apparatus of claim 1, comprising test circuitrydisposed on the semiconductor substrate outside the first semiconductordie.
 10. The apparatus of claim 1, wherein the first semiconductor dieincludes a microprocessor.
 11. The apparatus of claim 1, wherein thefirst semiconductor die includes read only memory.
 12. The apparatus ofclaim 1, comprising electrostatic damage protection circuitry disposedunder the first bond out pad.
 13. An apparatus comprising: a portion ofa semiconductor wafer; a first semiconductor die disposed on the portionof the semiconductor wafer; a first bond out pad disposed adjacent tothe first semiconductor die on the portion of the semiconductor wafer;and a first sawn semiconductor die disposed adjacent to the first bondout pad and at a first edge of the portion of the semiconductor wafer,wherein a part of the first sawn semiconductor die forms at least aportion of the first edge.
 14. The apparatus of claim 13, wherein thefirst semiconductor die includes a test die.
 15. The apparatus of claim13, comprising a second sawn semiconductor die disposed adjacent to thefirst semiconductor die and at a second edge of the portion of thesemiconductor wafer, wherein a part of the second sawn semiconductor dieforms at least a portion of the second edge.
 16. The apparatus of claim15, comprising a second bond out pad disposed between the firstsemiconductor die and the second sawn semiconductor die.
 17. Theapparatus of claim 13, comprising test circuitry disposed on the portionof a semiconductor wafer and adjacent the first semiconductor die.
 18. Asawn semiconductor wafer structure comprising: a first sawn edge and asecond sawn edge; a test die disposed between the first and second sawnedges; a first bond out pad disposed adjacent to the test die; and afirst sawn semiconductor die disposed adjacent to the first bond out padand at the first sawn edge, wherein at least a portion of the first sawnedge is a part of the first sawn semiconductor die.
 19. The sawnsemiconductor wafer structure of claim 18, comprising a second sawnsemiconductor die disposed adjacent to the test die and at the secondsawn edge, wherein at least a portion of the second sawn edge is a partof the second sawn semiconductor die.
 20. The sawn semiconductor waferstructure of claim 19, comprising a second bond out pad disposed betweenthe test die and the second sawn semiconductor die.